From 6f9f08f6eb3970f46ec96993779e723c6d3d929a Mon Sep 17 00:00:00 2001
From: Nina Engelhardt <nina.engelhardt@omnium-gatherum.de>
Date: Sun, 11 Aug 2013 23:53:33 +0200
Subject: [PATCH] add ternary operator sel ? a : b

---
 migen/fhdl/structure.py |  3 +++
 migen/fhdl/verilog.py   | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 9ef2cb324..e02866c37 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -94,6 +94,9 @@ class _Operator(Value):
 		self.op = op
 		self.operands = operands
 
+def Mux(sel, val1, val0):
+	return _Operator("m", [sel, val1, val0])
+
 class _Slice(Value):
 	def __init__(self, value, start, stop):
 		Value.__init__(self)
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index fa6ce3cfa..10bd7e372 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -58,6 +58,16 @@ def _printexpr(ns, node):
 					r2 = "$signed({1'd0, " + r2 + "})"
 			r = r1 + " " + node.op + " " + r2
 			s = s1 or s2
+		elif arity == 3:
+			assert node.op == "m"
+			r2, s2 = _printexpr(ns, node.operands[1])
+			r3, s3 = _printexpr(ns, node.operands[2])
+			if s2 and not s3:
+				r3 = "$signed({1'd0, " + r3 + "})"
+			if s3 and not s2:
+				r2 = "$signed({1'd0, " + r2 + "})"
+			r = r1 + " ? " + r2 + " : " + r3
+			s = s2 or s3
 		else:
 			raise TypeError
 		return "(" + r + ")", s