From cc21c662ca47490f6aacee66224a8a0767b5c5dd Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 18 Jun 2024 19:46:56 +0200 Subject: [PATCH 1/2] soc/cores/cpu/zynqmp/core.py: added csr into mem_map, added M_AXI_HPM0_FPD by default --- litex/soc/cores/cpu/zynqmp/core.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex/soc/cores/cpu/zynqmp/core.py b/litex/soc/cores/cpu/zynqmp/core.py index 01aeb5e8d..c45814b5c 100644 --- a/litex/soc/cores/cpu/zynqmp/core.py +++ b/litex/soc/cores/cpu/zynqmp/core.py @@ -39,6 +39,7 @@ class ZynqMP(CPU): def mem_map(self): return { "sram": 0x0000_0000, # DDR low in fact + "csr": 0xA000_0000, # ZynqMP M_AXI_HPM0_FPD (HPM0) "rom": 0xc000_0000, # Quad SPI memory } @@ -68,6 +69,7 @@ class ZynqMP(CPU): 'PSU__NUM_F2P0__INTR__INPUTS': 8, 'PSU__USE__IRQ1' : 1, # enable PL_PS_Group1 'PSU__NUM_F2P1__INTR__INPUTS': 8, + 'PSU__USE__M_AXI_GP1' : 0, } rst_n = Signal() self.cpu_params = dict( @@ -76,6 +78,11 @@ class ZynqMP(CPU): i_pl_ps_irq0 = self.interrupt[0: 8], i_pl_ps_irq1 = self.interrupt[8:16] ) + + # Use GP0 as peripheral bus / CSR + self.pbus = self.add_axi_gp_master(0) + self.periph_buses.append(self.pbus) + self.comb += ResetSignal("ps").eq(~rst_n) self.ps_tcl.append(f"set ps [create_ip -vendor xilinx.com -name zynq_ultra_ps_e -module_name {self.ps_name}]") From 146617eae8c67e0d10de4f1fe137bb78d7fef9bd Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 18 Jun 2024 22:13:12 +0200 Subject: [PATCH 2/2] soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default --- litex/soc/cores/cpu/zynq7000/core.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py index 628b234d4..ad449848d 100644 --- a/litex/soc/cores/cpu/zynq7000/core.py +++ b/litex/soc/cores/cpu/zynq7000/core.py @@ -40,6 +40,7 @@ class Zynq7000(CPU): def mem_map(self): return { "sram": 0x0010_0000, # DDR in fact + "csr": 0x4000_0000, # default GP0 address on Zynq "rom": 0xfc00_0000, } @@ -170,6 +171,10 @@ class Zynq7000(CPU): if ps7_sdio0_wp_pads is not None: self.cpu_params.update(i_SDIO0_WP = ps7_sdio0_wp_pads.wp) + # GP0 as Bus master ------------------------------------------------------------------------ + self.pbus = self.add_axi_gp_master() + self.periph_buses.append(self.pbus) + def set_ps7_xci(self, xci): # Add .xci as Vivado IP and set ps7_name from .xci filename. self.ps7_xci = xci @@ -177,9 +182,6 @@ class Zynq7000(CPU): self.platform.add_ip(xci) def add_ps7_config(self, config): - # Check that PS7 has been set. - if self.ps7_name is None: - raise Exception("Please set PS7 with set_ps7 method first.") # Config must be provided as a config, value dict. assert isinstance(config, dict) self.config.update(config)