diff --git a/misoclib/com/spi/test/spi_master_tb.py b/misoclib/com/spi/test/spi_master_tb.py
index 70d0f70df..f20aa19f2 100644
--- a/misoclib/com/spi/test/spi_master_tb.py
+++ b/misoclib/com/spi/test/spi_master_tb.py
@@ -83,4 +83,4 @@ class TB(Module):
         print("{:08x}".format(selfp.spi_master._miso.status))
 
 if __name__ == "__main__":
-    run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
\ No newline at end of file
+    run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
diff --git a/misoclib/cpu/lm32/__init__.py b/misoclib/cpu/lm32/__init__.py
index 76e99092d..e70afcee5 100644
--- a/misoclib/cpu/lm32/__init__.py
+++ b/misoclib/cpu/lm32/__init__.py
@@ -60,4 +60,4 @@ class LM32(Module):
                 "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
                 "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
                 "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
-        platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
\ No newline at end of file
+        platform.add_verilog_include_path(os.path.join("extcores", "lm32"))