From 738b45dcbd3415073714a909d37129dae3018323 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 16 Dec 2011 21:30:22 +0100 Subject: [PATCH] Support the new FHDL syntax --- milkymist/lm32/__init__.py | 22 +++++++++++----------- milkymist/norflash/__init__.py | 26 +++++++++++++------------- milkymist/uart/__init__.py | 18 +++++++++--------- tb/norflash/norflash_conv.py | 1 - 4 files changed, 33 insertions(+), 34 deletions(-) diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py index 46157f242..deae86c0e 100644 --- a/milkymist/lm32/__init__.py +++ b/milkymist/lm32/__init__.py @@ -1,13 +1,13 @@ -from migen.fhdl import structure as f +from migen.fhdl.structure import * from migen.bus import wishbone class Inst: def __init__(self): self.ibus = i = wishbone.Master("lm32i") self.dbus = d = wishbone.Master("lm32d") - f.declare_signal(self, "interrupt", f.BV(32)) - f.declare_signal(self, "ext_break") - self._inst = f.Instance("lm32_top", + declare_signal(self, "interrupt", BV(32)) + declare_signal(self, "ext_break") + self._inst = Instance("lm32_top", [("I_ADR_O", i.adr_o), ("I_DAT_O", i.dat_o), ("I_SEL_O", i.sel_o), @@ -15,7 +15,7 @@ class Inst: ("I_STB_O", i.stb_o), ("I_WE_O", i.we_o), ("I_CTI_O", i.cti_o), - ("I_LOCK_O", f.BV(1)), + ("I_LOCK_O", BV(1)), ("I_BTE_O", i.bte_o), ("D_ADR_O", d.adr_o), ("D_DAT_O", d.dat_o), @@ -24,18 +24,18 @@ class Inst: ("D_STB_O", d.stb_o), ("D_WE_O", d.we_o), ("D_CTI_O", d.cti_o), - ("D_LOCK_O", f.BV(1)), + ("D_LOCK_O", BV(1)), ("D_BTE_O", d.bte_o)], [("interrupt", self.interrupt), #("ext_break", self.ext_break), ("I_DAT_I", i.dat_i), ("I_ACK_I", i.ack_i), ("I_ERR_I", i.err_i), - ("I_RTY_I", f.BV(1)), + ("I_RTY_I", BV(1)), ("D_DAT_I", d.dat_i), ("D_ACK_I", d.ack_i), ("D_ERR_I", d.err_i), - ("D_RTY_I", f.BV(1))], + ("D_RTY_I", BV(1))], [], "clk_i", "rst_i", @@ -43,7 +43,7 @@ class Inst: def get_fragment(self): comb = [ - f.Assign(self._inst.ins["I_RTY_I"], 0), - f.Assign(self._inst.ins["D_RTY_I"], 0) + self._inst.ins["I_RTY_I"].eq(0), + self._inst.ins["D_RTY_I"].eq(0) ] - return f.Fragment(comb=comb, instances=[self._inst]) \ No newline at end of file + return Fragment(comb=comb, instances=[self._inst]) diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py index 5557e2529..55ffa6ea5 100644 --- a/milkymist/norflash/__init__.py +++ b/milkymist/norflash/__init__.py @@ -1,32 +1,32 @@ from functools import partial -from migen.fhdl import structure as f +from migen.fhdl.structure import * from migen.bus import wishbone from migen.corelogic import timeline class Inst: def __init__(self, adr_width, rd_timing): self.bus = wishbone.Slave("norflash") - d = partial(f.declare_signal, self) - d("adr", f.BV(adr_width-1)) - d("d", f.BV(16)) + d = partial(declare_signal, self) + d("adr", BV(adr_width-1)) + d("d", BV(16)) d("oe_n") d("we_n") d("ce_n") d("rst_n") self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i, - [(0, [f.Assign(self.adr, f.Cat(0, self.bus.adr_i[2:adr_width]))]), + [(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]), (rd_timing, [ - f.Assign(self.bus.dat_o[16:], self.d), - f.Assign(self.adr, f.Cat(1, self.bus.adr_i[2:adr_width]))]), + self.bus.dat_o[16:].eq(self.d), + self.adr.eq(Cat(1, self.bus.adr_i[2:adr_width]))]), (2*rd_timing, [ - f.Assign(self.bus.dat_o[:16], self.d), - f.Assign(self.bus.ack_o, 1)]), + self.bus.dat_o[:16].eq(self.d), + self.bus.ack_o.eq(1)]), (2*rd_timing+1, [ - f.Assign(self.bus.ack_o, 0)])]) + self.bus.ack_o.eq(0)])]) def get_fragment(self): - comb = [f.Assign(self.oe_n, 0), f.Assign(self.we_n, 1), - f.Assign(self.ce_n, 0), f.Assign(self.rst_n, 1)] - return f.Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \ + comb = [self.oe_n.eq(0), self.we_n.eq(1), + self.ce_n.eq(0), self.rst_n.eq(1)] + return Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n, self.rst_n}) \ + self.timeline.get_fragment() diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py index 87a4e2417..ba9e2de37 100644 --- a/milkymist/uart/__init__.py +++ b/milkymist/uart/__init__.py @@ -1,14 +1,14 @@ -from migen.fhdl import structure as f +from migen.fhdl.structure import * from migen.bus import csr class Inst: - def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=f.Constant(0)): + def __init__(self, csr_addr, clk_freq, baud=115200, break_en_default=Constant(0)): self.bus = csr.Slave("uart") - f.declare_signal(self, "tx") - f.declare_signal(self, "rx") - f.declare_signal(self, "irq") - f.declare_signal(self, "brk") - self._inst = f.Instance("uart", + declare_signal(self, "tx") + declare_signal(self, "rx") + declare_signal(self, "irq") + declare_signal(self, "brk") + self._inst = Instance("uart", [("csr_do", self.bus.d_o), ("uart_tx", self.tx), ("irq", self.irq), @@ -17,7 +17,7 @@ class Inst: ("csr_we", self.bus.we_i), ("csr_di", self.bus.d_i), ("uart_rx", self.rx)], - [("csr_addr", f.Constant(csr_addr, f.BV(4))), + [("csr_addr", Constant(csr_addr, BV(4))), ("clk_freq", clk_freq), ("baud", baud), ("break_en_default", break_en_default)], @@ -25,4 +25,4 @@ class Inst: "sys_rst") def get_fragment(self): - return f.Fragment(instances=[self._inst], pads={self.tx, self.rx}) + return Fragment(instances=[self._inst], pads={self.tx, self.rx}) diff --git a/tb/norflash/norflash_conv.py b/tb/norflash/norflash_conv.py index e093d5720..341f5e4cb 100644 --- a/tb/norflash/norflash_conv.py +++ b/tb/norflash/norflash_conv.py @@ -1,5 +1,4 @@ from migen.fhdl import verilog -from migen.fhdl import structure as f from migen.bus import wishbone from milkymist import norflash