From 45aa347e9a349fa4d265353f28bf38b3e4c8bf5b Mon Sep 17 00:00:00 2001
From: JoyBed <46244284+JoyBed@users.noreply.github.com>
Date: Sun, 16 Jun 2024 18:53:58 +0200
Subject: [PATCH] Add connect_mapped function

It allows connecting two different busses that has different memory mappings. Usefull when softcore in PL of Zynq7000 wants to access the DDR memory of the PS7 block.
---
 litex/soc/interconnect/axi/axi_full.py | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/litex/soc/interconnect/axi/axi_full.py b/litex/soc/interconnect/axi/axi_full.py
index 0c6c151fc..a49da18f9 100644
--- a/litex/soc/interconnect/axi/axi_full.py
+++ b/litex/soc/interconnect/axi/axi_full.py
@@ -137,6 +137,13 @@ class AXIInterface:
     def connect(self, slave, **kwargs):
         return connect_axi(self, slave, **kwargs)
 
+    def connect_mapped(self, slave, map_fct):
+        comb = []
+        comb += self.connect(slave, omit={"addr"})
+        comb += [slave.ar.addr.eq(map_fct(self.ar.addr))]
+        comb += [slave.aw.addr.eq(map_fct(self.aw.addr))]
+        return comb
+
     def layout_flat(self):
         return list(axi_layout_flat(self))