From 74140587c8ab4283a4e474d0ce505bfe79c0064e Mon Sep 17 00:00:00 2001 From: Sadullah Canakci Date: Tue, 10 Mar 2020 16:47:26 -0400 Subject: [PATCH] Create GETTING STARTED Rename GETTING STARTED to GETTING STARTED.md Update GETTING STARTED.md Update GETTING STARTED.md Update GETTING STARTED.md --- .../cores/cpu/blackparrot/GETTING STARTED.md | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 litex/soc/cores/cpu/blackparrot/GETTING STARTED.md diff --git a/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md b/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md new file mode 100644 index 000000000..47ea73734 --- /dev/null +++ b/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md @@ -0,0 +1,23 @@ +# Getting started + +## Running BP in LiteX + +cd $LITEX/litex/tools # the folder where litex simulator resides + +./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP --threads 4 --opt-level=O0 --trace --trace-start 0 + +#The above command will generate a dut.vcd file under build/BP/gateware folder. gtkwave works fine with the generated dut.vcd. + +## Additional Information + +The BlackParrot resides in $BP/pre-alpha-release/ + +core.py in $BP folder is the wrapper that integrates BP into LiteX. + +flist.verilator in $BP is all the files that litex_sim fetches for simulation. + +The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v + +The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v + +