From 741ecca5b4a06e296786ea7f50c75cef887a4d43 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 19 Feb 2015 11:41:54 +0100 Subject: [PATCH] la: fix intput_buffer clocking when clk_domain is not "sys" --- litescope/frontend/la.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/litescope/frontend/la.py b/litescope/frontend/la.py index 696a4ea45..cbe7dbc41 100644 --- a/litescope/frontend/la.py +++ b/litescope/frontend/la.py @@ -34,9 +34,13 @@ class LiteScopeLA(Module, AutoCSR): sink = self.sink # insert Buffer on sink (optional, can be used to improve timings) if self.with_input_buffer: - self.submodules.buffer = Buffer(self.sink.description) - self.comb += Record.connect(sink, self.buffer.d) - sink = self.buffer.q + input_buffer = Buffer(self.sink.description) + if self.clk_domain is not "sys": + self.submodules += RenameClockDomains(input_buffer, clk_domain) + else: + self.submodules += input_buffer + self.comb += Record.connect(sink, intput_buffer.d) + sink = intput_buffer.q # clock domain crossing (optional, required when capture_clk is not sys_clk) # XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation