From 7434376c07e2a697f65c09e809bfadcf557e4ac6 Mon Sep 17 00:00:00 2001 From: Mariusz Glebocki Date: Mon, 1 Jun 2020 13:58:44 +0200 Subject: [PATCH] test/test_targets: add arty_symbiflow Signed-off-by: Mariusz Glebocki --- test/test_targets.py | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/test/test_targets.py b/test/test_targets.py index 055954f10..ec767b15f 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -73,6 +73,13 @@ class TestTargets(unittest.TestCase): ]) self.assertEqual(errors, 0) + def test_arty_symbiflow(self): + from litex.boards.targets.arty_symbiflow import BaseSoC + errors = build_test([ + BaseSoC(**test_kwargs) + ]) + self.assertEqual(errors, 0) + # Kintex-7 def test_genesys2(self): from litex.boards.targets.genesys2 import BaseSoC @@ -112,21 +119,21 @@ class TestTargets(unittest.TestCase): def test_simple(self): platforms = [] # Xilinx - platforms += ["minispartan6"] # Spartan6 - platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7 - platforms += ["kc705", "genesys2"] # Kintex7 - platforms += ["kcu105"] # Kintex Ultrascale + platforms += ["minispartan6"] # Spartan6 + platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", "arty_symbiflow"] # Artix7 + platforms += ["kc705", "genesys2"] # Kintex7 + platforms += ["kcu105"] # Kintex Ultrascale # Altera/Intel - platforms += ["de0nano"] # Cyclone4 + platforms += ["de0nano"] # Cyclone4 # Lattice - platforms += ["tinyfpga_bx"] # iCE40 - platforms += ["machxo3"] # MachXO3 - platforms += ["versa_ecp5", "ulx3s"] # ECP5 + platforms += ["tinyfpga_bx"] # iCE40 + platforms += ["machxo3"] # MachXO3 + platforms += ["versa_ecp5", "ulx3s"] # ECP5 # Microsemi - platforms += ["avalanche"] # PolarFire + platforms += ["avalanche"] # PolarFire for p in platforms: with self.subTest(platform=p):