From 7456195775e9477a4eebfb3419f7f3b76fe97bd5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 21 Dec 2011 22:57:07 +0100 Subject: [PATCH] Consistent names --- README | 16 ++++++++-------- migen/fhdl/convtools.py | 16 ++++++++-------- migen/fhdl/structure.py | 28 ++++++++++++++-------------- migen/fhdl/verilog.py | 8 ++++---- 4 files changed, 34 insertions(+), 34 deletions(-) diff --git a/README b/README index 73fb5dd6f..8ff7538de 100644 --- a/README +++ b/README @@ -213,11 +213,11 @@ Assignments ----------- Assignments are represented with the _Assign object. Since using it directly would result in a cluttered syntax, the preferred technique for -assignments is to use the be() method provided by objects that can have a +assignments is to use the eq() method provided by objects that can have a value assigned to them. They are signals, and their combinations with the slice and concatenation operators. As an example, the statement: - a[0].be(b) + a[0].eq(b) is equivalent to: _Assign(_Slice(a, 0, 1), b) @@ -237,15 +237,15 @@ For convenience, there is also a Elif() method. Example: If(tx_count16 == 0, - tx_bitcount.be(tx_bitcount + 1), + tx_bitcount.eq(tx_bitcount + 1), If(tx_bitcount == 8, - self.tx.be(1) + self.tx.eq(1) ).Elif(tx_bitcount == 9, - self.tx.be(1), - tx_busy.be(0) + self.tx.eq(1), + tx_busy.eq(0) ).Else( - self.tx.be(tx_reg[0]), - tx_reg.be(Cat(tx_reg[1:], 0)) + self.tx.eq(tx_reg[0]), + tx_reg.eq(Cat(tx_reg[1:], 0)) ) ) diff --git a/migen/fhdl/convtools.py b/migen/fhdl/convtools.py index 12edaec90..0202f4f34 100644 --- a/migen/fhdl/convtools.py +++ b/migen/fhdl/convtools.py @@ -1,5 +1,5 @@ from migen.fhdl.structure import * -from migen.fhdl.structure import _Operator +from migen.fhdl.structure import _Operator, _Slice, _Assign, _StatementList class Namespace: def __init__(self): @@ -33,16 +33,16 @@ def list_signals(node): elif isinstance(node, _Operator): l = list(map(list_signals, node.operands)) return set().union(*l) - elif isinstance(node, Slice): + elif isinstance(node, _Slice): return list_signals(node.value) elif isinstance(node, Cat): l = list(map(list_signals, node.l)) return set().union(*l) elif isinstance(node, Replicate): return list_signals(node.v) - elif isinstance(node, Assign): + elif isinstance(node, _Assign): return list_signals(node.l) | list_signals(node.r) - elif isinstance(node, StatementList): + elif isinstance(node, _StatementList): l = list(map(list_signals, node.l)) return set().union(*l) elif isinstance(node, If): @@ -58,16 +58,16 @@ def list_signals(node): def list_targets(node): if isinstance(node, Signal): return {node} - elif isinstance(node, Slice): + elif isinstance(node, _Slice): return list_targets(node.value) elif isinstance(node, Cat): l = list(map(list_targets, node.l)) return set().union(*l) elif isinstance(node, Replicate): return list_targets(node.v) - elif isinstance(node, Assign): + elif isinstance(node, _Assign): return list_targets(node.l) - elif isinstance(node, StatementList): + elif isinstance(node, _StatementList): l = list(map(list_targets, node.l)) return set().union(*l) elif isinstance(node, If): @@ -92,7 +92,7 @@ def list_inst_outs(i): def is_variable(node): if isinstance(node, Signal): return node.variable - elif isinstance(node, Slice): + elif isinstance(node, _Slice): return is_variable(node.value) elif isinstance(node, Cat): arevars = list(map(is_variable, node.l)) diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index 50805abf1..0c4cfde2b 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -76,7 +76,7 @@ class Value: def __getitem__(self, key): if isinstance(key, int): - return Slice(self, key, key+1) + return _Slice(self, key, key+1) elif isinstance(key, slice): start = key.start or 0 stop = key.stop or self.bv.width @@ -84,19 +84,19 @@ class Value: stop = self.bv.width if key.step != None: raise KeyError - return Slice(self, start, stop) + return _Slice(self, start, stop) else: raise KeyError def eq(self, r): - return Assign(self, r) + return _Assign(self, r) class _Operator(Value): def __init__(self, op, operands): self.op = op self.operands = list(map(_cst, operands)) -class Slice(Value): +class _Slice(Value): def __init__(self, value, start, stop): self.value = value self.start = start @@ -155,12 +155,12 @@ class Signal(Value): # statements -class Assign: +class _Assign: def __init__(self, l, r): self.l = l self.r = _cst(r) -class StatementList: +class _StatementList: def __init__(self, l=None): if l is None: l = [] self.l = l @@ -168,15 +168,15 @@ class StatementList: class If: def __init__(self, cond, *t): self.cond = cond - self.t = StatementList(t) - self.f = StatementList() + self.t = _StatementList(t) + self.f = _StatementList() def Else(self, *f): - _insert_else(self, StatementList(f)) + _insert_else(self, _StatementList(f)) return self def Elif(self, cond, *t): - _insert_else(self, StatementList([If(cond, *t)])) + _insert_else(self, _StatementList([If(cond, *t)])) return self def _insert_else(obj, clause): @@ -189,7 +189,7 @@ def _insert_else(obj, clause): def _sl(x): if isinstance(x, list): - return StatementList(x) + return _StatementList(x) else: return x @@ -199,15 +199,15 @@ class Default: class Case: def __init__(self, test, *cases): self.test = test - self.cases = [(c[0], StatementList(c[1:])) for c in cases if not isinstance(c[0], Default)] + self.cases = [(c[0], _StatementList(c[1:])) for c in cases if not isinstance(c[0], Default)] self.default = None for c in cases: if isinstance(c[0], Default): if self.default is not None: raise ValueError - self.default = StatementList(c[1:]) + self.default = _StatementList(c[1:]) if self.default is None: - self.default = StatementList() + self.default = _StatementList() # diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 246702289..77665d17b 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -1,7 +1,7 @@ from functools import partial from migen.fhdl.structure import * -from migen.fhdl.structure import _Operator +from migen.fhdl.structure import _Operator, _Slice, _Assign, _StatementList from migen.fhdl.convtools import * def _printsig(ns, s): @@ -31,7 +31,7 @@ def _printexpr(ns, node): else: raise TypeError return "(" + r + ")" - elif isinstance(node, Slice): + elif isinstance(node, _Slice): if node.start + 1 == node.stop: sr = "[" + str(node.start) + "]" else: @@ -47,13 +47,13 @@ def _printexpr(ns, node): raise TypeError def _printnode(ns, level, node): - if isinstance(node, Assign): + if isinstance(node, _Assign): if is_variable(node.l): assignment = " = " else: assignment = " <= " return "\t"*level + _printexpr(ns, node.l) + assignment + _printexpr(ns, node.r) + ";\n" - elif isinstance(node, StatementList): + elif isinstance(node, _StatementList): return "".join(list(map(partial(_printnode, ns, level), node.l))) elif isinstance(node, If): r = "\t"*level + "if (" + _printexpr(ns, node.cond) + ") begin\n"