From 7513460572366868f5d96240a15be2881c63a444 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 19 Feb 2021 11:35:49 +0100
Subject: [PATCH] integration/soc/add_pcie: add with_msi parameter to allow
 disabling MSI when not required.

When just doing a PCIe to Wishbone Bridge (PCIeBone), DMAs and MSI are not required, with_msi
will allow disabling MSI when set to False.
---
 litex/soc/integration/soc.py | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 046157e05..8120b3ae0 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1574,7 +1574,7 @@ class LiteXSoC(SoC):
             self.sata_phy.crg.cd_sata_rx.clk)
 
     # Add PCIe -------------------------------------------------------------------------------------
-    def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8):
+    def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, with_msi=True):
         assert self.csr.data_width == 32
         assert not hasattr(self, f"{name}_endpoint")
 
@@ -1593,14 +1593,16 @@ class LiteXSoC(SoC):
         setattr(self.submodules, f"{name}_mmap", mmap)
 
         # MSI
-        msi = LitePCIeMSI()
-        setattr(self.submodules, f"{name}_msi", msi)
-        self.add_csr(f"{name}_msi")
-        self.comb += msi.source.connect(phy.msi)
-        self.msis = {}
+        if with_msi:
+            msi = LitePCIeMSI()
+            setattr(self.submodules, f"{name}_msi", msi)
+            self.add_csr(f"{name}_msi")
+            self.comb += msi.source.connect(phy.msi)
+            self.msis = {}
 
         # DMAs
         for i in range(ndmas):
+            assert with_msi
             dma = LitePCIeDMA(phy, endpoint,
                 with_buffering = True, buffering_depth=1024,
                 with_loopback  = True)
@@ -1611,9 +1613,10 @@ class LiteXSoC(SoC):
         self.add_constant("DMA_CHANNELS", ndmas)
 
         # Map/Connect IRQs
-        for i, (k, v) in enumerate(sorted(self.msis.items())):
-            self.comb += msi.irqs[i].eq(v)
-            self.add_constant(k + "_INTERRUPT", i)
+        if with_msi:
+            for i, (k, v) in enumerate(sorted(self.msis.items())):
+                self.comb += msi.irqs[i].eq(v)
+                self.add_constant(k + "_INTERRUPT", i)
 
         # Timing constraints
         self.platform.add_false_path_constraints(self.crg.cd_sys.clk, phy.cd_pcie.clk)