From 759367752caf21475b57d468a442635a87ac273b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 30 May 2020 15:21:32 +0200 Subject: [PATCH] wishbone/wishbone2csr: use wishbone.sel on CSR write. CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the 32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0. --- litex/soc/interconnect/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index be2f9f8df..75ed6f649 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -387,7 +387,7 @@ class Wishbone2CSR(Module): fsm.act("WRITE-READ", If(self.wishbone.cyc & self.wishbone.stb, self.csr.adr.eq(self.wishbone.adr), - self.csr.we.eq(self.wishbone.we), + self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)), NextState("ACK") ) )