From 75b000a32ff7c4706e34180b27b6e22a7a1e7be0 Mon Sep 17 00:00:00 2001 From: Jan Kowalewski Date: Tue, 25 Feb 2020 14:24:29 +0100 Subject: [PATCH] tools: litex_gen: fix missing UART pins --- litex/tools/litex_gen.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/litex/tools/litex_gen.py b/litex/tools/litex_gen.py index 465be327f..39904ef64 100755 --- a/litex/tools/litex_gen.py +++ b/litex/tools/litex_gen.py @@ -49,6 +49,15 @@ class LiteXCore(SoCMini): platform = Platform(_io) + # UART + if kwargs["with_uart"]: + platform.add_extension([ + ("serial", 0, + Subsignal("tx", Pins(1)), + Subsignal("rx", Pins(1)), + ) + ]) + # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))