From 75e230aae78390927f9b6f63e161103569d0fc95 Mon Sep 17 00:00:00 2001
From: Sergiusz Bazanski <q3k@q3k.org>
Date: Sun, 21 Jan 2018 21:46:25 +0000
Subject: [PATCH] Replace __riscv__ macros with __riscv.

The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
---
 litex/soc/software/bios/main.c      | 2 +-
 litex/soc/software/bios/sdram.c     | 2 +-
 litex/soc/software/common.mak       | 2 +-
 litex/soc/software/libbase/system.c | 6 +++---
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 64ca2e0bb..082aa62fb 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -497,7 +497,7 @@ int main(int i, char **c)
 	printf("\e[1mLM32\e[0m\n");
 #elif __or1k__
 	printf("\e[1mOR1K\e[0m\n");
-#elif __riscv__
+#elif __riscv
 	printf("\e[1mRISC-V\n");
 #else
 	printf("\e[1mUnknown\e[0m\n");
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 5b1ebd701..7550282ad 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -18,7 +18,7 @@ static void cdelay(int i)
 		__asm__ volatile("nop");
 #elif defined (__or1k__)
 		__asm__ volatile("l.nop");
-#elif defined (__riscv__)
+#elif defined (__riscv)
 		__asm__ volatile("nop");
 #else
 #error Unsupported architecture
diff --git a/litex/soc/software/common.mak b/litex/soc/software/common.mak
index 11e8fc385..82cb37c0c 100644
--- a/litex/soc/software/common.mak
+++ b/litex/soc/software/common.mak
@@ -1,7 +1,7 @@
 TARGET_PREFIX=$(TRIPLE)-
 
 RM ?= rm -f
-PYTHON ?= python3
+PYTHON ?= python
 
 ifeq ($(CLANG),1)
 CC_normal      := clang -target $(TRIPLE) -integrated-as
diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index 4306b9320..f23dced81 100644
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -34,7 +34,7 @@ void flush_cpu_icache(void)
 
 	for (i = 0; i < cache_size; i += cache_block_size)
 		mtspr(SPR_ICBIR, i);
-#elif defined (__riscv__)
+#elif defined (__riscv)
 	/* no instruction cache */
 	asm volatile("nop");
 #else
@@ -65,7 +65,7 @@ void flush_cpu_dcache(void)
 
 	for (i = 0; i < cache_size; i += cache_block_size)
 		mtspr(SPR_DCBIR, i);
-#elif defined (__riscv__)
+#elif defined (__riscv)
 	/* no data cache */
 	asm volatile("nop");
 #else
@@ -86,7 +86,7 @@ void flush_l2_cache(void)
 		__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
 #elif defined (__or1k__)
 		__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
-#elif defined (__riscv__)
+#elif defined (__riscv)
 	/* FIXME */
 	asm volatile("nop");
 #else