From 75ee8a5db9267bed42051f0ed1a6d493f68fd925 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Mar 2015 01:59:55 +0100 Subject: [PATCH] sdram/phy/simphy: OK with DDR3 --- misoclib/mem/sdram/phy/simphy.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py index 1dc818e26..6ec396261 100644 --- a/misoclib/mem/sdram/phy/simphy.py +++ b/misoclib/mem/sdram/phy/simphy.py @@ -2,10 +2,8 @@ # License: BSD # SDRAM simulation PHY at DFI level -# Status: -# - tested against software memtest with SDR/DDR/LPDDR/DDR2 with Verilator. +# tested with SDR/DDR/DDR2/LPDDR/DDR3 # TODO: -# - test with DDR3 # - add $display support to Migen and manage timing violations? from migen.fhdl.std import *