diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index f36f344f3..a92faa6a8 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1259,8 +1259,6 @@ class LiteXSoC(SoC):
             sdcard_pads = self.platform.request(name)
 
         # Core
-        if hasattr(sdcard_pads, "rst"):
-            self.comb += sdcard_pads.rst.eq(0)
         self.submodules.sdphy   = SDPHY(sdcard_pads, self.platform.device, self.clk_freq)
         self.submodules.sdcore  = SDCore(self.sdphy)
         self.add_csr("sdphy")