From 7613c90fcdc9a7ef69a90389d9043ae968b48442 Mon Sep 17 00:00:00 2001
From: Ilia Sergachev <ilia@sergachev.ch>
Date: Sun, 24 Jul 2022 23:02:41 +0200
Subject: [PATCH] sim: enable relative include paths for verilator

---
 litex/build/sim/core/Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 486419bae..585ef6e03 100644
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -51,7 +51,8 @@ sim: $(OBJS_SIM) | mkdir
 		--output-split-ctrace 500 \
 		$(INC_DIR) \
 		-Wno-BLKANDNBLK \
-		-Wno-WIDTH
+		-Wno-WIDTH \
+		--relative-includes
 	make -j$(JOBS) -C $(OBJ_DIR) -f Vsim.mk Vsim
 
 .PHONY: modules