From 7618b845338072066a9d2c92774d59fbb3fd3f75 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 27 Jun 2019 23:20:12 +0200
Subject: [PATCH] soc_core: use new way to add wisbone slave (now prefered)
---
litex/soc/integration/soc_core.py | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 8f703ec83..a65920448 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -422,13 +422,12 @@ class SoCCore(Module):
self._memory_regions.append((name, origin, length))
- def register_mem(self, name, address, interface, size=None):
- self.add_wb_slave(mem_decoder(address), interface)
- if size is not None:
- self.add_memory_region(name, address, size)
+ def register_mem(self, name, address, interface, size=0x10000000):
+ self.add_wb_slave(address, interface, size)
+ self.add_memory_region(name, address, size)
def register_rom(self, interface, rom_size=0xa000):
- self.add_wb_slave(mem_decoder(self.soc_mem_map["rom"]), interface)
+ self.add_wb_slave(self.soc_mem_map["rom"], interface, rom_size)
self.add_memory_region("rom", self.cpu_reset_address, rom_size)
def get_memory_regions(self):