From 7627dadb9b317564ec3585741bbd982d8a0f072d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 29 Dec 2020 09:29:23 +0100 Subject: [PATCH] tools/litex_json2dts/soc_controller: add workaround for VexRiscv-SMP. We need to fix https://github.com/litex-hub/linux-on-litex-vexriscv/issues/176 to be able to switch to soc-controller with VexRiscv-SMP. --- litex/tools/litex_json2dts.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/litex/tools/litex_json2dts.py b/litex/tools/litex_json2dts.py index 942536d72..c2ddc4fd3 100755 --- a/litex/tools/litex_json2dts.py +++ b/litex/tools/litex_json2dts.py @@ -141,7 +141,17 @@ def generate_dts(d, initrd_start=None, initrd_size=None, polling=False): # SoC Controller ------------------------------------------------------------------------------- - dts += """ + if cpu_name == "vexriscv smp-linux": # FIXME: remove when kernel will be generated from litex-rebase. + dts += """ + soc_ctrl0: soc_controller@{soc_ctrl_csr_base:x} {{ + compatible = "litex,soc_controller"; + reg = <0x{soc_ctrl_csr_base:x} 0xc>; + status = "okay"; + }}; +""".format(soc_ctrl_csr_base=d["csr_bases"]["ctrl"]) + + else: + dts += """ soc_ctrl0: soc_controller@{soc_ctrl_csr_base:x} {{ compatible = "litex,soc-controller"; reg = <0x{soc_ctrl_csr_base:x} 0xc>;