From 7662ec553111b6a6de38ef171e039e69848a986e Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 25 Oct 2021 17:11:10 +0200
Subject: [PATCH] clock/efinix_trion: Replace ' with ".

---
 litex/soc/cores/clock/efinix_trion.py | 58 +++++++++++++--------------
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/litex/soc/cores/clock/efinix_trion.py b/litex/soc/cores/clock/efinix_trion.py
index 260382f7b..d226f9536 100644
--- a/litex/soc/cores/clock/efinix_trion.py
+++ b/litex/soc/cores/clock/efinix_trion.py
@@ -28,42 +28,42 @@ class TRIONPLL(Module):
 
         block = {}
 
-        block['type'] = 'PLL'
-        block['name'] = self.pll_name
-        block['clk_out'] = []
+        block["type"] = "PLL"
+        block["name"] = self.pll_name
+        block["clk_out"] = []
 
-        pll_locked_name = self.pll_name + '_locked'
-        block['locked'] = pll_locked_name
+        pll_locked_name = self.pll_name + "_locked"
+        block["locked"] = pll_locked_name
         io = self.platform.add_iface_io(pll_locked_name)
         self.comb += self.locked.eq(io)
 
-        block['reset'] = ''
+        block["reset"] = ""
         if with_reset:
-            pll_reset_name = self.pll_name + '_reset'
-            block['reset'] = pll_reset_name
+            pll_reset_name = self.pll_name + "_reset"
+            block["reset"] = pll_reset_name
             io = self.platform.add_iface_io(pll_reset_name)
             self.comb += io.eq(self.reset)
 
         self.platform.toolchain.ifacewriter.blocks.append(block)
 
-    def register_clkin(self, clkin, freq, name= ''):
+    def register_clkin(self, clkin, freq, name= ""):
         block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
 
-        block['input_clock_name'] = self.platform.get_pin_name(clkin)
+        block["input_clock_name"] = self.platform.get_pin_name(clkin)
 
         # If clkin has a pin number, PLL clock input is EXTERNAL
         if self.platform.get_pin_location(clkin):
             pad_name = self.platform.get_pin_location(clkin)[0]
             # PLL v1 needs pin name
             pin_name = self.platform.parser.get_gpio_instance_from_pin(pad_name)
-            if pin_name.count('_') == 2:
-                pin_name = pin_name.rsplit('_', 1)[0]
+            if pin_name.count("_") == 2:
+                pin_name = pin_name.rsplit("_", 1)[0]
 
             self.platform.delete(clkin)
 
             #tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
             #sdc = self.platform.toolchain.additional_sdc_commands
-            #sdc.append(tpl.format(clk=block['input_clock_name'], period=1/freq))
+            #sdc.append(tpl.format(clk=block["input_clock_name"], period=1/freq))
 
             try:
                 (pll_res, clock_no) = self.platform.parser.get_pll_inst_from_pin(pad_name)
@@ -71,29 +71,29 @@ class TRIONPLL(Module):
                 self.logger.error("Cannot find a pll with {} as input".format(pad_name))
                 quit()
 
-            block['input_clock'] = 'EXTERNAL'
-            block['input_clock_pad'] = pin_name
-            block['resource'] = pll_res
-            block['clock_no'] = clock_no
-            self.logger.info("Clock source: {}, using EXT_CLK{}".format(block['input_clock'], clock_no))
+            block["input_clock"] = "EXTERNAL"
+            block["input_clock_pad"] = pin_name
+            block["resource"] = pll_res
+            block["clock_no"] = clock_no
+            self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
             self.platform.get_pll_resource(pll_res)
         else:
-            block['input_clock'] = 'INTERNAL'
-            block['resource'] = self.platform.get_free_pll_resource()
-            block['input_signal'] = name
-            self.logger.info("Clock source: {}".format(block['input_clock']))
+            block["input_clock"] = "INTERNAL"
+            block["resource"] = self.platform.get_free_pll_resource()
+            block["input_signal"] = name
+            self.logger.info("Clock source: {}".format(block["input_clock"]))
 
-        block['input_freq'] = freq
+        block["input_freq"] = freq
 
-        self.logger.info("Using {}".format(block['resource']))
+        self.logger.info("Using {}".format(block["resource"]))
 
-    def create_clkout(self, cd, freq, phase=0, margin=1e-2, name='', with_reset=False):
+    def create_clkout(self, cd, freq, phase=0, margin=1e-2, name="", with_reset=False):
         assert self.nclkouts < self.nclkouts_max
 
-        if name != '':
+        if name != "":
             clk_out_name = name
         else:
-            clk_out_name = '{}_CLKOUT{}'.format(self.pll_name, self.nclkouts)
+            clk_out_name = "{}_CLKOUT{}".format(self.pll_name, self.nclkouts)
 
         if cd != None:
             self.platform.add_extension([(clk_out_name, 0, Pins(1))])
@@ -110,11 +110,11 @@ class TRIONPLL(Module):
         self.nclkouts += 1
 
         block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
-        block['clk_out'].append([clk_out_name, freq, phase, margin])
+        block["clk_out"].append([clk_out_name, freq, phase, margin])
 
     def extra(self, extra):
         block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
-        block['extra'] = extra
+        block["extra"] = extra
 
     def compute_config(self):
         pass