diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0f8df306c..1c912e211 100755
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -871,7 +871,7 @@ class SoC(Module):
             colorer("added", color="green")))
         setattr(self.submodules, name, SoCController(**kwargs))
 
-    def add_ram(self, name, origin, size, contents=[], mode="rw"):
+    def add_ram(self, name, origin, size, contents=[], mode="rwx"):
         ram_cls = {
             "wishbone": wishbone.SRAM,
             "axi-lite": axi.AXILiteSRAM,
@@ -894,7 +894,7 @@ class SoC(Module):
         if contents != []:
             self.add_config(f"{name}_INIT", 1)
 
-    def add_rom(self, name, origin, size, contents=[], mode="r"):
+    def add_rom(self, name, origin, size, contents=[], mode="rx"):
         self.add_ram(name, origin, size, contents, mode=mode)
 
     def init_rom(self, name, contents=[], auto_size=True):
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index d7208903f..7329fc775 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -78,7 +78,7 @@ class SoCCore(LiteXSoC):
 
         # ROM parameters
         integrated_rom_size      = 0,
-        integrated_rom_mode      = "r",
+        integrated_rom_mode      = "rx",
         integrated_rom_init      = [],
 
         # SRAM parameters