diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index a7f005245..45800d2e8 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -644,7 +644,6 @@ class SoCController(Module, AutoCSR): class SoC(Module): mem_map = {} def __init__(self, platform, sys_clk_freq, - bus_standard = "wishbone", bus_data_width = 32, bus_address_width = 32, @@ -856,6 +855,9 @@ class SoC(Module): colorer(self.bus_interconnect.__class__.__name__), colorer(len(self.bus.masters)), colorer(len(self.bus.slaves)))) + self.add_constant("CONFIG_BUS_STANDARD", self.bus.standard.upper()) + self.add_constant("CONFIG_BUS_DATA_WIDTH", self.bus.data_width) + self.add_constant("CONFIG_BUS_ADDRESS_WIDTH", self.bus.address_width) # SoC CSR Interconnect --------------------------------------------------------------------- self.submodules.csr_bankarray = csr_bus.CSRBankArray(self, diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index 077064459..e2181b761 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -103,13 +103,20 @@ int main(int i, char **c) printf("\e[1mCPU\e[0m: %s @ %dMHz\n", CONFIG_CPU_HUMAN_NAME, CONFIG_CLOCK_FREQUENCY/1000000); - printf("\e[1mROM\e[0m: %dKB\n", ROM_SIZE/1024); - printf("\e[1mSRAM\e[0m: %dKB\n", SRAM_SIZE/1024); + printf("\e[1mBUS\e[0m: %s %d-bit / %dGiB\n", + CONFIG_BUS_STANDARD, + CONFIG_BUS_DATA_WIDTH, + (1 << (CONFIG_BUS_ADDRESS_WIDTH - 30))); + printf("\e[1mCSR\e[0m: %d-bit / %d-bit aligned\n", + CONFIG_CSR_DATA_WIDTH, + CONFIG_CSR_ALIGNMENT); + printf("\e[1mROM\e[0m: %dKiB\n", ROM_SIZE/1024); + printf("\e[1mSRAM\e[0m: %dKiB\n", SRAM_SIZE/1024); #ifdef CONFIG_L2_SIZE - printf("\e[1mL2\e[0m: %dKB\n", CONFIG_L2_SIZE/1024); + printf("\e[1mL2\e[0m: %dKiB\n", CONFIG_L2_SIZE/1024); #endif #ifdef MAIN_RAM_SIZE - printf("\e[1mMAIN-RAM\e[0m: %dKB\n", MAIN_RAM_SIZE/1024); + printf("\e[1mMAIN-RAM\e[0m: %dKiB\n", MAIN_RAM_SIZE/1024); #endif printf("\n");