From 774a55a2aa7cefe6f617cce38697822508325c27 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 19 Feb 2020 14:58:55 +0100 Subject: [PATCH] soc_core: fix missing init on main_ram --- litex/soc/integration/soc_core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 7ba7b49ec..e3f78e0d6 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -168,7 +168,7 @@ class SoCCore(LiteXSoC): # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) if integrated_main_ram_size: - self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size) + self.add_ram("main_ram", self.mem_map["main_ram"], integrated_main_ram_size, integrated_main_ram_init) # Add Identifier if ident != "":