From 77a6f580e2a0cdc7168cf29841e5ead8ee9f13ce Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Feb 2015 09:46:52 +0100 Subject: [PATCH] gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts --- misoclib/gensoc/__init__.py | 12 ++++++++++++ targets/mlabs_video.py | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 46068cccc..332310c48 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -91,10 +91,22 @@ class GenSoC(Module): raise FinalizeError self._wb_slaves.append((address_decoder, interface)) + def check_cpu_memory_region(self, name, origin): + for n, o, l in self.cpu_memory_regions: + if n == name or o == origin: + raise ValueError("Memory region conflict between {} and {}".format(n, name)) + def add_cpu_memory_region(self, name, origin, length): + self.check_cpu_memory_region(name, origin) self.cpu_memory_regions.append((name, origin, length)) + def check_cpu_csr_region(self, name, origin): + for n, o, l, obj in self.cpu_csr_regions: + if n == name or o == origin: + raise ValueError("CSR region conflict between {} and {}".format(n, name)) + def add_cpu_csr_region(self, name, origin, busword, obj): + self.check_cpu_csr_region(name, origin) self.cpu_csr_regions.append((name, origin, busword, obj)) def do_finalize(self): diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 4e921fee4..b30b86b2d 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -128,7 +128,7 @@ TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG; class FramebufferSoC(MiniSoC): csr_map = { - "fb": 11, + "fb": 12, } csr_map.update(MiniSoC.csr_map)