diff --git a/examples/basic/memory.py b/examples/basic/memory.py
index 30d0430cc..3d0aab457 100644
--- a/examples/basic/memory.py
+++ b/examples/basic/memory.py
@@ -1,23 +1,11 @@
 from migen.fhdl.structure import *
 from migen.fhdl import verilog
 
-d = 100
-d_b = bits_for(d-1)
-w = 32
+mem = Memory(32, 100, init=[5, 18, 32])
+p1 = mem.get_port(write_capable=True, we_granularity=8)
+p2 = mem.get_port(has_re=True, clock_domain="rd")
 
-a1 = Signal(BV(d_b))
-d1 = Signal(BV(w))
-we1 = Signal(BV(4))
-dw1 = Signal(BV(w))
-re = Signal()
-p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
-
-a2 = Signal(BV(d_b))
-d2 = Signal(BV(w))
-re2 = Signal()
-p2 = MemoryPort(a2, d2, re=re2, clock_domain="rd")
-
-mem = Memory(w, d, p1, p2, init=[5, 18, 32])
 f = Fragment(memories=[mem])
-v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
+v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w,
+	p2.adr, p2.dat_r, p2.re})
 print(v)