diff --git a/litex/soc/cores/cpu/vexriscv_smp/irq.h b/litex/soc/cores/cpu/vexriscv_smp/irq.h
index 4dceaf8b8..c50d44679 100644
--- a/litex/soc/cores/cpu/vexriscv_smp/irq.h
+++ b/litex/soc/cores/cpu/vexriscv_smp/irq.h
@@ -18,7 +18,7 @@ extern "C" {
 #define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger
 #define PLIC_CLAIM   0xf0e00004L // Claim & completion register address
 
-#define PLIC_EXT_IRQ_BASE 1 // CHECKME/FIXME.
+#define PLIC_EXT_IRQ_BASE 0 // CHECKME/FIXME.
 
 static inline unsigned int irq_getie(void)
 {
@@ -32,17 +32,17 @@ static inline void irq_setie(unsigned int ie)
 
 static inline unsigned int irq_getmask(void)
 {
-	return *((unsigned int *)PLIC_ENABLED) >> 1;
+	return *((unsigned int *)PLIC_ENABLED) >> PLIC_EXT_IRQ_BASE;
 }
 
 static inline void irq_setmask(unsigned int mask)
 {
-	*((unsigned int *)PLIC_ENABLED) = mask << 1;
+	*((unsigned int *)PLIC_ENABLED) = mask << PLIC_EXT_IRQ_BASE;
 }
 
 static inline unsigned int irq_pending(void)
 {
-	return *((unsigned int *)PLIC_PENDING) >> 1;
+	return *((unsigned int *)PLIC_PENDING) >> PLIC_EXT_IRQ_BASE;
 }
 
 #ifdef __cplusplus
diff --git a/litex/soc/software/libbase/isr.c b/litex/soc/software/libbase/isr.c
index eb2fe7ae5..359ac1cc1 100644
--- a/litex/soc/software/libbase/isr.c
+++ b/litex/soc/software/libbase/isr.c
@@ -29,7 +29,7 @@ void isr(void)
     onetime++;
   }
 }
-#elif defined(__rocket__) || defined(__openc906__)
+#elif defined(__rocket__) || defined(__openc906__) || defined(__vexriscv_smp__)
 
 // PLIC initialization.
 void plic_init(void);