diff --git a/CHANGES b/CHANGES
index ed4399a74..836fead16 100644
--- a/CHANGES
+++ b/CHANGES
@@ -27,6 +27,7 @@
 	- Revert to a single crt0 (avoid ctr/xip variants).
 	- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
 	- Add AXI-Lite bus standard support.
+	- Add VexRiscv SMP CPU support.
 
 	[> API changes/Deprecation
 	--------------------------
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 4f73c141d..2fe60b253 100644
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -12,10 +12,7 @@ from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
-from litedram.common import LiteDRAMNativePort
-
 import os
-import os.path
 
 
 CPU_VARIANTS = {
@@ -257,6 +254,7 @@ class VexRiscvSMP(CPU):
                 )
             ]
 
+        from litedram.common import LiteDRAMNativePort
         if "mp" in variant:
             ncpus = int(variant[-2]) # FIXME
             for n in range(ncpus):
diff --git a/litex_setup.py b/litex_setup.py
index 9eb91a7f9..d1e9a6caf 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -46,7 +46,7 @@ repos = [
     ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-serv",        ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True, None)),
-    ("pythondata-cpu-vexriscv_smp",("https://github.com/litex-hub/", True,  True, None)),
+    ("pythondata-cpu-vexriscv-smp",("https://github.com/litex-hub/", True,  True, None)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-minerva",     ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True, 0xba76652)),