diff --git a/mibuild/platforms/minispartan6.py b/mibuild/platforms/minispartan6.py
index 7ef468ac0..17bbe4492 100644
--- a/mibuild/platforms/minispartan6.py
+++ b/mibuild/platforms/minispartan6.py
@@ -99,8 +99,8 @@ _connectors = [
 class Platform(XilinxISEPlatform):
 	default_clk_name = "clk50"
 	default_clk_period = 20
-	def __init__(self):
-		XilinxISEPlatform.__init__(self, "xc6slx9-3-ftg256", _io,
+	def __init__(self, device="xc6slx9"):
+		XilinxISEPlatform.__init__(self, device+"-3-ftg256", _io,
 			lambda p: SimpleCRG(p, "clk50", None), _connectors)
 
 	def create_programmer(self):