From 79913e8614a08dbaff25fdcc35a564863fa515c9 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 Apr 2020 09:18:39 +0200
Subject: [PATCH] litex.build: update from migen.genlib.io litex.build.io.

---
 litex/boards/targets/minispartan6.py | 2 +-
 litex/build/altera/common.py         | 4 ++--
 litex/build/lattice/common.py        | 3 +--
 litex/build/xilinx/common.py         | 2 +-
 litex/soc/cores/clock.py             | 3 ++-
 litex/soc/cores/hyperbus.py          | 3 ++-
 6 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 2903a5074..408ed442c 100755
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -9,9 +9,9 @@ import argparse
 from fractions import Fraction
 
 from migen import *
-from migen.genlib.io import DDROutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DDROutput
 from litex.boards.platforms import minispartan6
 
 from litex.soc.cores.clock import *
diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py
index 45770984b..252f5fbd4 100644
--- a/litex/build/altera/common.py
+++ b/litex/build/altera/common.py
@@ -2,12 +2,12 @@
 # This file is Copyright (c) 2019 vytautasb <v.buitvydas@limemicro.com>
 # License: BSD
 
+from migen import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance
-from migen.genlib.io import DifferentialInput, DifferentialOutput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from migen.fhdl.structure import *
+from litex.build.io import *
 
 # DifferentialInput --------------------------------------------------------------------------------
 
diff --git a/litex/build/lattice/common.py b/litex/build/lattice/common.py
index 6b340c8db..52286dda0 100644
--- a/litex/build/lattice/common.py
+++ b/litex/build/lattice/common.py
@@ -6,10 +6,9 @@
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Instance, Tristate
 from migen.fhdl.bitcontainer import value_bits_sign
-from migen.genlib.io import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.gen.io import *
+from litex.build.io import *
 
 # ECP5 AsyncResetSynchronizer ----------------------------------------------------------------------
 
diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index bc6c96d50..0017f623e 100644
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -13,8 +13,8 @@ from migen.fhdl.specials import Instance
 from migen.fhdl.module import Module
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.io import *
 
+from litex.build.io import *
 from litex.build import tools
 
 # Colorama -----------------------------------------------------------------------------------------
diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 2ff7668c9..97f83c7ba 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -8,9 +8,10 @@ import math
 import logging
 
 from migen import *
-from migen.genlib.io import DifferentialInput
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.build.io import DifferentialInput
+
 from litex.soc.integration.soc import colorer
 from litex.soc.interconnect.csr import *
 
diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py
index c1dc0b8cd..cfc813104 100644
--- a/litex/soc/cores/hyperbus.py
+++ b/litex/soc/cores/hyperbus.py
@@ -4,7 +4,8 @@
 
 from migen import *
 from migen.genlib.misc import timeline
-from migen.genlib.io import DifferentialOutput
+
+from litex.build.io import DifferentialOutput
 
 from litex.soc.interconnect import wishbone