From 7a87d4e262436b9f693a5a1fce29c36f7247b8d9 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Mon, 24 Feb 2020 14:39:44 +0100 Subject: [PATCH] Fix ECP5PLL VCO frequency range See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5 and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing". --- litex/soc/cores/clock.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index cab8bfcef..63a9edaa6 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -507,7 +507,7 @@ class ECP5PLL(Module): clko_div_range = (1, 128+1) clki_freq_range = ( 8e6, 400e6) clko_freq_range = (3.125e6, 400e6) - vco_freq_range = ( 550e6, 1250e6) + vco_freq_range = ( 400e6, 800e6) def __init__(self): self.reset = Signal()