From 7a9cf57cfe5555c3bb2f54d2907465d7b0537c1e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 14 Oct 2016 17:49:04 +0200 Subject: [PATCH] boards/targets/sim: fix --- litex/boards/targets/sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 9c892911c..0f0d657d0 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -51,7 +51,7 @@ class BaseSoC(SoCSDRAM): self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings, - ControllerSettings(with_refresh=False)) + controller_settings=ControllerSettings(with_refresh=False)) # reduce memtest size to speed up simulation self.add_constant("MEMTEST_DATA_SIZE", 8*1024) self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)