From 7ad2f7081bf1c6d7d33f11b1045fbd6e350503d3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 13 Feb 2013 23:59:35 +0100 Subject: [PATCH] m1crg: fix signal names --- load.jtag | 2 +- verilog/m1crg/m1crg.v | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/load.jtag b/load.jtag index 8fbe5621d..0379fef0a 100644 --- a/load.jtag +++ b/load.jtag @@ -2,4 +2,4 @@ cable milkymist detect instruction CFG_OUT 000100 BYPASS instruction CFG_IN 000101 BYPASS -pld load build/soc.bit +pld load build/top.bit diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v index f32f3efd2..8ec923ead 100644 --- a/verilog/m1crg/m1crg.v +++ b/verilog/m1crg/m1crg.v @@ -204,7 +204,7 @@ ODDR2 #( .INIT(1'b0), .SRTYPE("SYNC") ) sd_clk_forward_p ( - .Q(sd_clk_out_p), + .Q(ddr_clk_pad_p), .C0(clk2x_270), .C1(~clk2x_270), .CE(1'b1), @@ -218,7 +218,7 @@ ODDR2 #( .INIT(1'b0), .SRTYPE("SYNC") ) sd_clk_forward_n ( - .Q(sd_clk_out_n), + .Q(ddr_clk_pad_n), .C0(clk2x_270), .C1(~clk2x_270), .CE(1'b1), @@ -233,7 +233,7 @@ ODDR2 #( */ always @(posedge pllout4) - eth_clk_pad <= ~eth_clk_pad; + eth_phy_clk_pad <= ~eth_phy_clk_pad; /* Let the synthesizer insert the appropriate buffers */ assign eth_rx_clk = eth_rx_clk_pad;