diff --git a/targets/ppro.py b/targets/ppro.py
index 1ec8c513a..3bd29ef2b 100644
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -63,7 +63,7 @@ class BaseSoC(SDRAMSoC):
 	def __init__(self, platform, **kwargs):
 		clk_freq = 80*1000*1000
 		SDRAMSoC.__init__(self, platform, clk_freq,
-			cpu_reset_address=0x160000, **kwargs)
+			cpu_reset_address=0x60000, **kwargs)
 
 		self.submodules.crg = _CRG(platform, clk_freq)