From 7b413352c20f753cbc9c2d94ebd291697ad8e72e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 20 Aug 2024 12:04:23 +0200 Subject: [PATCH] soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__. --- litex/soc/cores/hyperbus.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 3381aacd3..e4427bb88 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -44,7 +44,7 @@ class HyperRAM(LiteXModule): pads (Record) : Platform pads of HyperRAM. bus (wishbone.Interface) : Wishbone Interface. """ - def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=None, with_csr=True): + def __init__(self, pads, latency=6, latency_mode="variable", sys_clk_freq=10e6, with_csr=True): self.pads = pads self.bus = bus = wishbone.Interface(data_width=32, address_width=32, addressing="word") @@ -128,8 +128,6 @@ class HyperRAM(LiteXModule): raise ValueError # Burst Timer ------------------------------------------------------------------------------ - if sys_clk_freq is None: - sys_clk_freq = 10e6 # Defaults to 10MHz if not specified. self.burst_timer = burst_timer = WaitTimer(sys_clk_freq * self.tCSM) # Clock Generation (sys_clk/4) -------------------------------------------------------------