From 7b5515ced477c43f330c0a646dae2c63d9d230e5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 19 Jun 2023 23:02:50 +0200 Subject: [PATCH] cores/pwm: Simplify pwm generation and avoid potential glitch on reset. --- litex/soc/cores/pwm.py | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/litex/soc/cores/pwm.py b/litex/soc/cores/pwm.py index 20818ecfe..bdc762981 100644 --- a/litex/soc/cores/pwm.py +++ b/litex/soc/cores/pwm.py @@ -47,14 +47,7 @@ class PWM(Module, AutoCSR): ] # PWM Width logic. - sync += [ - pwm.eq(0), - If(self.enable & ~self.reset, - If(counter < self.width, - pwm.eq(1) - ) - ) - ] + sync += pwm.eq(self.enable & (counter < self.width)) if with_csr: self.add_csr(clock_domain)