From 7b7334fc1799c64f8dd5e195a1b827607035a959 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 14 May 2024 11:41:21 +0200 Subject: [PATCH] cpu/vexiiriscv update --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 1c6cfea1a..3ccf9441e 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -130,7 +130,7 @@ class VexiiRiscv(CPU): print(args) if args.update_repo != "no": - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "b4e86579" if args.update_repo=="recommended" else None) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "c330b794" if args.update_repo=="recommended" else None)