diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 3700bf44c..5a1afedcb 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -18,6 +18,9 @@ class VexRiscv(Module, AutoCSR):
         variant = "std_debug" if variant == "debug" else variant
         variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
         assert variant in variants, "Unsupported variant %s" % variant
+        self.platform = platform
+        self.variant = variant
+        self.external_variant = None
         self.reset = Signal()
         self.ibus = ibus = wishbone.Interface()
         self.dbus = dbus = wishbone.Interface()
@@ -59,9 +62,6 @@ class VexRiscv(Module, AutoCSR):
         if "debug" in variant:
             self.add_debug()
 
-        # add verilog sources
-        self.add_sources(platform, variant)
-
     def add_debug(self):
         debug_reset = Signal()
 
@@ -162,5 +162,11 @@ class VexRiscv(Module, AutoCSR):
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, cpu_filename))
 
+    def use_external_variant(self, variant_filename):
+        self.external_variant = True
+        self.platform.add_source(variant_filename)
+
     def do_finalize(self):
+        if not self.external_variant:
+            self.add_sources(self.platform, self.variant)
         self.specials += Instance("VexRiscv", **self.cpu_params)