From 7bcebf4cdd34704f6e379e9d5e8da7d7fb8c82bc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 30 Dec 2020 12:24:48 +0100 Subject: [PATCH] cpu/microwatt: improve/fix XICS controller integration for variants with irq. --- litex/soc/cores/cpu/microwatt/core.py | 11 +++++------ litex/soc/integration/soc.py | 5 +++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 3b7258284..bd3643fb6 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -16,7 +16,6 @@ from litex.soc.interconnect.csr import * from litex.gen.common import reverse_bytes from litex.soc.cores.cpu import CPU - CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq"] class Microwatt(CPU): @@ -108,16 +107,12 @@ class Microwatt(CPU): # add vhdl sources self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) - # add XICS controller - if "irq" in variant: - self.add_xics() - def set_reset_address(self, reset_address): assert not hasattr(self, "reset_address") self.reset_address = reset_address assert reset_address == 0x00000000 - def add_xics(self): + def add_xics(self, soc, soc_region_cls): self.submodules.xics = XICSSlave( platform = self.platform, variant = self.variant, @@ -125,6 +120,10 @@ class Microwatt(CPU): int_level_in = self.interrupt, endianness = self.endianness ) + xicsicp_region = soc_region_cls(origin=soc.mem_map.get("hostxicsicp", 0xc3ff0000), size=4096, cached=False) + xicsics_region = soc_region_cls(origin=soc.mem_map.get("hostxicsics", 0xc3ff1000), size=4096, cached=False) + soc.bus.add_slave(name="hostxicsicp", slave=self.xics.icp_bus, region=xicsicp_region) + soc.bus.add_slave(name="hostxicsics", slave=self.xics.ics_bus, region=xicsics_region) @staticmethod def add_sources(platform, use_ghdl_yosys_plugin=False): diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index e369ec446..79e1f3c52 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -895,6 +895,11 @@ class SoC(Module): if hasattr(self.ctrl, "reset"): self.comb += self.cpu.reset.eq(self.ctrl.reset) self.add_config("CPU_RESET_ADDR", reset_address) + + # Specific Microwatt IROs integration FIXME (remove or provide generic integration method) + if isinstance(self.cpu, cpu.Microwatt) and "irq" in variant: + self.cpu.add_xics(self, SoCRegion) + # Add constants self.add_config("CPU_TYPE", str(name)) self.add_config("CPU_VARIANT", str(variant.split('+')[0]))