diff --git a/litex/soc/cores/clock/xilinx_s6.py b/litex/soc/cores/clock/xilinx_s6.py
index b44ff14ee..e64a48fa8 100644
--- a/litex/soc/cores/clock/xilinx_s6.py
+++ b/litex/soc/cores/clock/xilinx_s6.py
@@ -37,7 +37,6 @@ class S6PLL(XilinxClocking):
             p_BANDWIDTH      = "OPTIMIZED",
             p_COMPENSATION   = "INTERNAL",
             i_RST            = self.reset,
-            i_PWRDWN         = self.power_down,
             o_LOCKED         = self.locked,
 
             # VCO.