From 7bd06d178f33c2bdce28f648e553dcd1d87d7878 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 2 Sep 2021 15:12:16 +0200
Subject: [PATCH] cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input
 on PLL_ADV).

---
 litex/soc/cores/clock/xilinx_s6.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/litex/soc/cores/clock/xilinx_s6.py b/litex/soc/cores/clock/xilinx_s6.py
index b44ff14ee..e64a48fa8 100644
--- a/litex/soc/cores/clock/xilinx_s6.py
+++ b/litex/soc/cores/clock/xilinx_s6.py
@@ -37,7 +37,6 @@ class S6PLL(XilinxClocking):
             p_BANDWIDTH      = "OPTIMIZED",
             p_COMPENSATION   = "INTERNAL",
             i_RST            = self.reset,
-            i_PWRDWN         = self.power_down,
             o_LOCKED         = self.locked,
 
             # VCO.