From 7c3fbf1d06163a2e840b0c68c44fd9ec6b8e54e0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <jboczar@antmicro.com>
Date: Mon, 7 Sep 2020 15:29:02 +0200
Subject: [PATCH] sim: improve tracing reset value and behaviour with
 sim_debug=False

---
 litex/build/sim/core/veril.cpp |  2 +-
 litex/tools/litex_sim.py       | 17 ++++++++++++-----
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index a5f0cb333..ee435d37d 100644
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -56,7 +56,7 @@ extern "C" void litex_sim_init_tracer(void *vsim, long start, long end)
 
 extern "C" void litex_sim_tracer_dump()
 {
-  static int last_enabled = -1;
+  static int last_enabled = 0;
   bool dump_enabled = true;
 
   if (g_sim != nullptr) {
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 0ba304d50..5ad3b030d 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -183,6 +183,7 @@ class SimSoC(SoCCore):
         with_i2c              = False,
         with_sdcard           = False,
         sim_debug             = False,
+        trace_reset_on        = False,
         **kwargs):
         platform     = Platform()
         sys_clk_freq = int(1e6)
@@ -317,7 +318,9 @@ class SimSoC(SoCCore):
 
         # Simulatio debugging ----------------------------------------------------------------------
         if sim_debug:
-            platform.add_debug(self)
+            platform.add_debug(self, reset=1 if trace_reset_on else 0)
+        else:
+            self.comb += platform.trace.eq(1)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -343,8 +346,8 @@ def main():
     parser.add_argument("--with-sdcard",          action="store_true",     help="Enable SDCard support")
     parser.add_argument("--trace",                action="store_true",     help="Enable Tracing")
     parser.add_argument("--trace-fst",            action="store_true",     help="Enable FST tracing (default=VCD)")
-    parser.add_argument("--trace-start",          default=0,               help="Cycle to start tracing")
-    parser.add_argument("--trace-end",            default=-1,              help="Cycle to end tracing")
+    parser.add_argument("--trace-start",          default="0",             help="Time to start tracing (ps)")
+    parser.add_argument("--trace-end",            default="-1",            help="Time to end tracing (ps)")
     parser.add_argument("--opt-level",            default="O3",            help="Compilation optimization level")
     parser.add_argument("--sim-debug",            action="store_true",     help="Add simulation debugging modules")
     args = parser.parse_args()
@@ -383,6 +386,9 @@ def main():
     if args.with_i2c:
         sim_config.add_module("spdeeprom", "i2c")
 
+    trace_start = int(float(args.trace_start))
+    trace_end = int(float(args.trace_end))
+
     # SoC ------------------------------------------------------------------------------------------
     soc = SimSoC(
         with_sdram     = args.with_sdram,
@@ -392,6 +398,7 @@ def main():
         with_i2c       = args.with_i2c,
         with_sdcard    = args.with_sdcard,
         sim_debug      = args.sim_debug,
+        trace_reset_on = trace_start > 0 or trace_end > 0,
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
         **soc_kwargs)
     if args.ram_init is not None:
@@ -416,8 +423,8 @@ def main():
             opt_level   = args.opt_level,
             trace       = args.trace,
             trace_fst   = args.trace_fst,
-            trace_start = int(args.trace_start),
-            trace_end   = int(args.trace_end)
+            trace_start = trace_start,
+            trace_end   = trace_end
         )
         if args.with_analyzer:
             soc.analyzer.export_csv(vns, "analyzer.csv")