From 7c67bac723c0f7ae6a2820358c933bcfa2cfa5a5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 Jan 2019 10:28:24 +0100 Subject: [PATCH] soc/cores/cpu/vexriscv: set default variant to None in add_sources --- litex/soc/cores/cpu/lm32/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index b79a7fd6c..e7b18bf64 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -66,7 +66,7 @@ class LM32(Module): self.add_sources(platform, variant) @staticmethod - def add_sources(platform, variant): + def add_sources(platform, variant=None): vdir = os.path.join( os.path.abspath(os.path.dirname(__file__)), "verilog") platform.add_sources(os.path.join(vdir, "submodule", "rtl"),