From 7caed5679027743e16091e7b0481ca796394e636 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Apr 2021 14:36:10 +0200 Subject: [PATCH] cores/timer: Expose uptime_cycles and allow multiple calls to add_uptime. --- litex/soc/cores/timer.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/timer.py b/litex/soc/cores/timer.py index 808fcc74a..545fa7e51 100644 --- a/litex/soc/cores/timer.py +++ b/litex/soc/cores/timer.py @@ -16,6 +16,7 @@ from litex.soc.integration.doc import ModuleDoc # Timer -------------------------------------------------------------------------------------------- class Timer(Module, AutoCSR, ModuleDoc): + with_uptime = False """Timer Provides a generic Timer core. @@ -87,11 +88,13 @@ class Timer(Module, AutoCSR, ModuleDoc): self.comb += self.ev.zero.trigger.eq(value != 0) def add_uptime(self, width=64): + if self.with_uptime: return + self.with_uptime = True self._uptime_latch = CSRStorage(description="Write a ``1`` to latch current Uptime cycles to ``uptime_cycles`` register.") self._uptime_cycles = CSRStatus(width, description="Latched Uptime since power-up (in ``sys_clk`` cycles).") # # # - uptime_cycles = Signal(width, reset_less=True) + self.uptime_cycles = uptime_cycles = Signal(width, reset_less=True) self.sync += uptime_cycles.eq(uptime_cycles + 1) - self.sync += If(self._uptime_latch.re, self._uptime_cycles.status.eq(uptime_cycles)) + self.sync += If(self._uptime_latch.re, self._uptime_cycles.status.eq(uptime_cycles)) \ No newline at end of file