From 7cee8e10fd437eb8c8f03cfe268f0658f29f71b1 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 14 Nov 2023 11:24:17 +0100 Subject: [PATCH] build/efinix/ifacewriter: allowing PLL to have LVDS_RX as input type --- litex/build/efinix/ifacewriter.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py index 5609a93b8..95177b2c1 100644 --- a/litex/build/efinix/ifacewriter.py +++ b/litex/build/efinix/ifacewriter.py @@ -277,7 +277,11 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block["input_freq"] / 1e6) cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name) - if block["input_clock"] == "EXTERNAL": + if block["input_clock"] == "LVDS_RX": + cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \ + .format(name, block["resource"], block["input_clock_pad"], block["clock_no"]) + cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name) + elif block["input_clock"] == "EXTERNAL": # PLL V1 has a different configuration if partnumber[0:2] in ["T4", "T8"]: cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_res="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \