From 7d278854d56cd7d9df1632835d22e590c3250540 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 22 Apr 2019 09:37:00 +0200 Subject: [PATCH] global: switch to VexRiscv as the default CPU VexRiscv can now replace LM32 for almost all usecases and we now have better software support with RISC-V. --- README | 35 +++++++++++-------------------- litex/soc/integration/soc_core.py | 2 +- test/test_targets.py | 19 ++++++++--------- 3 files changed, 22 insertions(+), 34 deletions(-) diff --git a/README b/README index bee291c59..88357cb0f 100644 --- a/README +++ b/README @@ -92,32 +92,21 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10 ----------------------------------------- 0. Install Python 3.5+ and FPGA vendor's development tools. -1. Get litex_setup.py script and execute: - ./litex_setup.py init install - This will clone and install Migen, LiteX and LiteX's cores. - To update all repositories execute: - ./litex_setup.py update +1. Install Migen/LiteX and the LiteX's cores: + wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py + ./litex_setup.py init install + Later, if you need to update all repositories: + ./litex_setup.py update -2. Compile and install binutils. Take the latest version from GNU. - mkdir build && cd build - ../configure --target=lm32-elf - make - make install +2. Install a RISC-V toolchain: + wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz + tar -xvf riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz + export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin/ -3. (Optional, only if you want to use a lm32 CPU in you SoC) - Compile and install GCC. Take gcc-core and gcc-g++ from GNU - (version 4.5 or >=4.9). - rm -rf libstdc++-v3 - mkdir build && cd build - ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \ - --disable-libssp - make - make install - -4. Build the target of your board...: +3. Build the target of your board...: Go to boards/targets and execute the target you want to build -5. ... and/or install Verilator and test LiteX on your computer: +4. ... and/or install Verilator and test LiteX on your computer: Download and install Verilator: http://www.veripool.org/ On Fedora: sudo dnf install libevent-devel json-c-devel @@ -125,7 +114,7 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10 sudo apt install libevent-dev libjson-c-dev run: litex_sim -6. Run a terminal program on the board's serial port at 115200 8-N-1. +5. Run a terminal program on the board's serial port at 115200 8-N-1. You should get the BIOS prompt. [> Contact diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index b8897d00b..e0e10673d 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -141,7 +141,7 @@ class SoCCore(Module): "csr": 0x60000000, # (default shadow @0xe0000000) } def __init__(self, platform, clk_freq, - cpu_type="lm32", cpu_reset_address=0x00000000, cpu_variant=None, + cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, integrated_rom_size=0, integrated_rom_init=[], integrated_sram_size=4096, integrated_main_ram_size=0, integrated_main_ram_init=[], diff --git a/test/test_targets.py b/test/test_targets.py index 06a635822..73f0cc772 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -18,53 +18,52 @@ def build_test(socs): class TestTargets(unittest.TestCase): - kwargs = {"cpu_type": "vexriscv"} # altera boards def test_de0nano(self): from litex.boards.targets.de0nano import BaseSoC - errors = build_test([BaseSoC(**self.kwargs)]) + errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) # xilinx boards def test_minispartan6(self): from litex.boards.targets.minispartan6 import BaseSoC - errors = build_test([BaseSoC(**self.kwargs)]) + errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) def test_arty(self): from litex.boards.targets.arty import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) + errors = build_test([BaseSoC(), EthernetSoC()]) self.assertEqual(errors, 0) def test_nexys4ddr(self): from litex.boards.targets.nexys4ddr import BaseSoC - errors = build_test([BaseSoC(**self.kwargs)]) + errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) def test_nexys_video(self): from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) + errors = build_test([BaseSoC(), EthernetSoC()]) self.assertEqual(errors, 0) def test_genesys2(self): from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) + errors = build_test([BaseSoC(), EthernetSoC()]) self.assertEqual(errors, 0) def test_kc705(self): from litex.boards.targets.kc705 import BaseSoC, EthernetSoC - errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)]) + errors = build_test([BaseSoC(), EthernetSoC()]) self.assertEqual(errors, 0) # lattice boards def test_versa_ecp5(self): from litex.boards.targets.versa_ecp5 import BaseSoC - errors = build_test([BaseSoC(**self.kwargs)]) + errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) def test_versa_ulx3s(self): from litex.boards.targets.ulx3s import BaseSoC - errors = build_test([BaseSoC(**self.kwargs)]) + errors = build_test([BaseSoC()]) self.assertEqual(errors, 0) # build simple design for all platforms