From 7df1d75dee8392b87b1cfc0f22e5218ff807c008 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Dec 2014 23:19:48 +0100 Subject: [PATCH] use max_count of 16 and clean up --- lib/sata/__init__.py | 4 ++-- lib/sata/command/__init__.py | 2 +- platforms/kc705.py | 6 +++--- targets/test.py | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/lib/sata/__init__.py b/lib/sata/__init__.py index b347a324f..de72c7ef4 100644 --- a/lib/sata/__init__.py +++ b/lib/sata/__init__.py @@ -4,7 +4,7 @@ from lib.sata.transport import SATATransport from lib.sata.command import SATACommand class SATACON(Module): - def __init__(self, phy, sector_size=512, max_count=8): + def __init__(self, phy, sector_size=512, max_count=16): self.sector_size = sector_size self.max_count = max_count @@ -12,6 +12,6 @@ class SATACON(Module): self.link = SATALink(phy) self.transport = SATATransport(self.link) - self.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count) + self.command = SATACommand(self.transport, sector_size, max_count) self.sink, self.source = self.command.sink, self.command.source diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py index 97522b997..9c7e35cf8 100644 --- a/lib/sata/command/__init__.py +++ b/lib/sata/command/__init__.py @@ -102,7 +102,7 @@ class SATACommandRX(Module): ### cmd_fifo = SyncFIFO(command_rx_cmd_description(32), 2) # Note: ideally depth=1 - data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), sector_size*max_count//4, buffered=True)) + data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), (sector_size*max_count//4), buffered=True)) self.submodules += cmd_fifo, data_fifo def test_type(name): diff --git a/platforms/kc705.py b/platforms/kc705.py index 46ebe3673..0dcf075db 100644 --- a/platforms/kc705.py +++ b/platforms/kc705.py @@ -128,9 +128,9 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs): except ConstraintError: pass self.add_platform_command(""" -create_clock -name sys_clk -period 5 [get_nets sys_clk] -create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk] -create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk] +create_clock -name sys_clk -period 10 [get_nets sys_clk] +create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk] +create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk] diff --git a/targets/test.py b/targets/test.py index b50e19ba4..0b6c5a6ce 100644 --- a/targets/test.py +++ b/targets/test.py @@ -166,8 +166,8 @@ class TestDesign(UART2WB, AutoCSR): UART2WB.__init__(self, platform, clk_freq) self.crg = _CRG(platform) - self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2") - self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8) + self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2") + self.sata_con = SATACON(self.sata_phy) self.bist = SATABIST(self.sata_con)