diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 0caba97b6..c65dcf23b 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -10,6 +10,7 @@ from migen import *
 from litex.boards.platforms import nexys4ddr
 
 from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
@@ -53,7 +54,7 @@ class _CRG(Module):
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
-class BaseSoC(SoCSDRAM):
+class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs):
         platform = nexys4ddr.Platform()
 
@@ -70,10 +71,15 @@ class BaseSoC(SoCSDRAM):
                 nphases      = 2,
                 sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
-            sdram_module = MT47H64M16(sys_clk_freq, "1:2")
-            self.register_sdram(self.ddrphy,
-                geom_settings   = sdram_module.geom_settings,
-                timing_settings = sdram_module.timing_settings)
+            self.add_sdram("sdram",
+                phy                     = self.ddrphy,
+                module                  = MT47H64M16(sys_clk_freq, "1:2"),
+                origin                  = self.mem_map["main_ram"],
+                size                    = kwargs["max_sdram_size"],
+                l2_cache_size           = kwargs["l2_size"],
+                l2_cache_min_data_width = kwargs["min_l2_data_width"],
+                l2_cache_reverse        = True
+            )
 
         # Ethernet ---------------------------------------------------------------------------------
         if with_ethernet:
diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 6c6f3c702..9eecaa567 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -54,7 +54,7 @@ def soc_sdram_args(parser):
     # L2 Cache
     parser.add_argument("--l2-size", default=8192,
                         help="L2 cache size (default=8192)")
-    parser.add_argument("--min-l2-datawidth", default=128,
+    parser.add_argument("--min-l2-data-width", default=128,
                         help="Minimum L2 cache datawidth (default=128)")
 
     # SDRAM