diff --git a/litex/soc/cores/bitbang.py b/litex/soc/cores/bitbang.py
index 325c6d475..a5f5f10f8 100644
--- a/litex/soc/cores/bitbang.py
+++ b/litex/soc/cores/bitbang.py
@@ -22,6 +22,7 @@ class I2CMaster(Module, AutoCSR):
 
     Software get back SDA value with the read CSRStatus (_r).
     """
+    init        = []
     pads_layout = [("scl", 1), ("sda", 1)]
     def __init__(self, pads=None):
         if pads is None:
@@ -51,6 +52,9 @@ class I2CMaster(Module, AutoCSR):
             i  = self._r.fields.sda
         )
 
+    def add_init(self, addr, init, init_addr_len=1):
+        self.init.append((addr, init, init_addr_len))
+
 class I2CMasterSim(I2CMaster):
     """I2C Master Bit-Banging for Verilator simulation
 
@@ -77,6 +81,16 @@ class I2CMasterSim(I2CMaster):
             )
         ]
 
+# I2C Master Init Collection  ----------------------------------------------------------------------
+
+def collect_i2c_init(soc):
+    i2c_init = []
+    for name, obj in xdir(soc, True):
+        if isinstance(obj, I2CMaster) and hasattr(obj, "init"):
+           for addr, init, init_addr_len in obj.init:
+                i2c_init.append((name, addr, init, init_addr_len))
+    return i2c_init
+
 # SPI Master Bit-Banging ---------------------------------------------------------------------------
 
 class SPIMaster(Module, AutoCSR):
diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index fd78d4a76..8b9a089b5 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -204,7 +204,8 @@ class Builder:
         write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents)
 
         # Generate I2C command/value table
-        i2c_contents = export.get_i2c_header(self.soc.i2c_init)
+        from litex.soc.cores.bitbang import collect_i2c_init
+        i2c_contents = export.get_i2c_header(collect_i2c_init(self.soc))
         write_to_file(os.path.join(self.generated_dir, "i2c.h"), i2c_contents)
 
         # Generate Git SHA1 of tools to git.h
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 630d3dfa8..6aaae1e0f 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -174,9 +174,6 @@ class SoCCore(LiteXSoC):
         # Wishbone Slaves.
         self.wb_slaves = {}
 
-        # I2C initialisation tables
-        self.i2c_init = []
-
         # Modules instances ------------------------------------------------------------------------
 
         # Add SoCController
@@ -272,9 +269,6 @@ class SoCCore(LiteXSoC):
     def add_csr_region(self, name, origin, busword, obj):
         self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
 
-    def add_i2c_init_table(self, dev, i2c_addr, table, addr_len=1):
-        self.i2c_init.append((dev, i2c_addr, table, addr_len))
-
     # Finalization ---------------------------------------------------------------------------------
 
     def do_finalize(self):