diff --git a/README b/README
index c310196d7..0443353d4 100644
--- a/README
+++ b/README
@@ -44,6 +44,8 @@ external Rx/Tx pins to be ready to debug or control all your Wishbone peripheral
 - Logic analyser with LiteScopeLA:
   - Various triggering modules: Term, Range, Edge (add yours! :)
   - Run Length Encoder to "compress" data and increase recording depth
+  - Subsampling
+  - Storage qualifier
   - Data storage in block rams
 
 [> Possibles improvements
diff --git a/litescope/core/storage.py b/litescope/core/storage.py
index be1ac211e..ce1cf35d5 100644
--- a/litescope/core/storage.py
+++ b/litescope/core/storage.py
@@ -85,6 +85,7 @@ class LiteScopeRecorderUnit(Module):
 		self.data_sink = data_sink = Sink(data_layout(dw))
 
 		self.trigger = Signal()
+		self.qualifier = Signal()
 		self.length = Signal(bits_for(depth))
 		self.offset = Signal(bits_for(depth))
 		self.done = Signal()
@@ -119,7 +120,11 @@ class LiteScopeRecorderUnit(Module):
 			If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
 		)
 		fsm.act("POST_HIT_RECORDING",
-			fifo.sink.stb.eq(data_sink.stb),
+			If(self.qualifier,
+				fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
+			).Else(
+				fifo.sink.stb.eq(data_sink.stb)
+			),
 			fifo.sink.data.eq(data_sink.data),
 			data_sink.ack.eq(fifo.sink.ack),
 
@@ -131,6 +136,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
 		LiteScopeRecorderUnit.__init__(self, dw, depth)
 
 		self._trigger = CSR()
+		self._qualifier = CSRStorage()
 		self._length = CSRStorage(bits_for(depth))
 		self._offset = CSRStorage(bits_for(depth))
 		self._done = CSRStatus()
@@ -143,6 +149,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
 
 		self.comb += [
 			self.trigger.eq(self._trigger.re),
+			self.qualifier.eq(self._qualifier.storage),
 			self.length.eq(self._length.storage),
 			self.offset.eq(self._offset.storage),
 			self._done.status.eq(self.done),
diff --git a/litescope/frontend/la.py b/litescope/frontend/la.py
index 4defc02ac..104ced680 100644
--- a/litescope/frontend/la.py
+++ b/litescope/frontend/la.py
@@ -63,7 +63,11 @@ class LiteScopeLA(Module, AutoCSR):
 				Record.connect(rle.source, self.recorder.data_sink)
 			]
 		else:
-			self.comb += Record.connect(sink, self.recorder.data_sink)
+			self.submodules.delay_buffer = Buffer(self.sink.description)
+			self.comb += [
+				Record.connect(sink, self.delay_buffer.d),
+				Record.connect(self.delay_buffer.q, self.recorder.data_sink)
+			]
 
 	def export(self, vns, filename):
 		def format_line(*args):
diff --git a/litescope/host/driver.py b/litescope/host/driver.py
index 4c305a0e1..904b9fef1 100644
--- a/litescope/host/driver.py
+++ b/litescope/host/driver.py
@@ -187,6 +187,9 @@ class LiteScopeLADriver():
 	def configure_subsampler(self, n):
 		self.subsampler_value.write(n-1)
 
+	def configure_qualifier(self, v):
+		self.recorder_qualifier.write(v)
+
 	def configure_rle(self, v):
 		self.rle_enable.write(v)
 
diff --git a/test/test_la.py b/test/test_la.py
index 4904aa081..48b7a9ba2 100644
--- a/test/test_la.py
+++ b/test/test_la.py
@@ -8,7 +8,8 @@ la = LiteScopeLADriver(wb.regs, "la", debug=True)
 cond = {"cnt0"	:	128} # trigger on cnt0 = 128
 la.configure_term(port=0, cond=cond)
 la.configure_sum("term")
-la.configure_subsampler(16)
+la.configure_subsampler(1)
+la.configure_qualifier(1)
 la.run(offset=128, length=256)
 
 while not la.done():