From 7fa1cd72a8d354409087dc8b001a5eeb7a4385d2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 19 Mar 2015 00:24:30 +0100 Subject: [PATCH] fhdl/verilog: fix dummy signal initial event --- migen/fhdl/verilog.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index ee4206628..bc0504414 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -184,7 +184,8 @@ def _printcomb(f, ns, display_run): syn_on = "// synthesis translate_on\n" dummy_s = Signal(name_override="dummy_s") r += syn_off - r += "reg " + _printsig(ns, dummy_s) + " = 1'd0;\n" + r += "reg " + _printsig(ns, dummy_s) + ";\n" + r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n" r += syn_on groups = group_by_targets(f.comb)