From 7fcdd94cd410c5b2cd55c5548d3d44b0f0ca28a7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 30 Jun 2017 19:40:54 +0200 Subject: [PATCH] soc/interconnect/stream_packet: reset_less optimizations --- litex/soc/interconnect/stream_packet.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py index 577f3e707..8e4dff15e 100644 --- a/litex/soc/interconnect/stream_packet.py +++ b/litex/soc/interconnect/stream_packet.py @@ -163,7 +163,7 @@ class Packetizer(Module): dw = len(self.sink.data) - header_reg = Signal(header.length*8) + header_reg = Signal(header.length*8, reset_less=True) header_words = (header.length*8)//dw load = Signal() shift = Signal() @@ -253,6 +253,7 @@ class Depacketizer(Module): dw = len(sink.data) + header_reg = Signal(header.length*8, reset_less=True) header_words = (header.length*8)//dw shift = Signal() @@ -269,13 +270,14 @@ class Depacketizer(Module): if header_words == 1: self.sync += \ If(shift, - self.header.eq(sink.data) + header_reg.eq(sink.data) ) else: self.sync += \ If(shift, - self.header.eq(Cat(self.header[dw:], sink.data)) + header_reg.eq(Cat(header_reg[dw:], sink.data)) ) + self.comb += self.header.eq(header_reg) fsm = FSM(reset_state="IDLE") self.submodules += fsm